1. Field of the Invention
This invention relates to a display device, and more particularly to a liquid crystal display (LCD) device.
2. Description of the Related Art
Generally, a liquid crystal display (LCD) device uses a pixel array matrix disposed at intersections of gate and data lines, thereby display image data corresponding to video signals.
FIG. 1 is a schematic block diagram showing an LCD according to the conventional art. In FIG. 1, the conventional LCD includes a liquid crystal display panel 12 for displaying image data corresponding to video signals, a host controller 1 for generating video signals 2R, 2G and 2B, a vertical synchronizing signal V, and a horizontal synchronizing signal H, a data driver 8 for applying the video signals to data lines DL of the liquid crystal display panel 12, a data controller 4 arranged between the host controller 1 and the data driver 8 to apply the video signals 2R, 2G and 2B from the host controller 1 to the data driver 8, a gate driver 10 for applying a scanning signal to gate lines GL of the liquid crystal display panel 12, and a timing controller 6 arranged between the host controller 1 and the gate driver 10 to apply the vertical and horizontal synchronizing signals V and H from the host controller 1 to the data driver 10 and the gate driver 8, respectively.
The host controller 1 applies the video signals 2R, 2G and 2B stored in a video RAM (not shown) to the data controller 4. In addition, the host controller 1 includes a vertical synchronizing signal oscillator 3 for creating the vertical synchronizing signal V, and a horizontal synchronizing signal oscillator 5 for creating the horizontal synchronizing signal H. The vertical synchronizing signal oscillator 3 generates a 60 Hz vertical synchronizing signal V and applies it to the timing controller 6. The horizontal synchronizing signal oscillator 5 generates a horizontal synchronizing signal H and applies it the timing controller 4.
The data controller 4 receives the video signals 2R, 2G and 2B from the host controller 1 to apply the video signals 2R, 2G and 2B to the data driver 8 on a serial transmission basis. The timing controller 6 applies the 60 Hz vertical synchronizing signal V from the host controller 1 to the gate driver 10, and applies the horizontal synchronizing signal H from the host controller 1 to the data driver 8.
The horizontal synchronizing signal H is generated by the horizontal synchronizing signal oscillator 5 according to the following equation:H=Vertical resolution *V* 1.05  (1)
The data driver 8 is synchronized with the horizontal synchronizing signal H from the timing controller 6 to apply video signals 2R′, 2G′ and 2B′ from the data controller 4 to the data lines DL of the liquid crystal display panel 12, line by line. More specifically, the data driver 8 latches each of red (R), green (G) and blue (B) data inputted sequentially in conformity to a clock of the horizontal synchronizing signal H from the timing controller 6, thereby changing the timing system from the dot at a timing scanning into the line at a timing scanning. Subsequently, the data driver 8 transfers data stored in a first latch (not shown) to a second latch (not shown) in conformity to a transfer enable signal every period of the horizontal synchronizing signal H. The data stored in the second latch is converted into an analog voltage by an analog to digital converter (not shown) and then is applied to the data lines DL via a current buffer (not shown).
The gate driver 10 is synchronized with the vertical synchronizing signal V from the timing controller 6 to sequentially create a gate pulse for applying the video signals 2R′, 2G′ and 2B′ from the data lines DL to each pixel, thereby applying the gate pulse to gate lines GL of the liquid crystal display panel 12. More specifically, the gate driver 10 includes a shift register (not shown) for shifting a start pulse, in which a logic input value of the vertical synchronizing signal V is high, sequentially at one line time intervals, a level shifter (not shown) for converting an output logic level of the shift register into an on/off voltage of the gate line GL, and a current buffer (not shown) for amplifying a current in corresponding to a load of the gate line GL. Such a configuration sequentially applies a scanning pulse, which is an on/off signal, to the gate lines GL.
More specifically, the shift register of the data driver 8 is supplied with video signals sequentially pixel by pixel to store the video signals corresponding to the data lines DL. Subsequently, the gate driver 10 outputs a gate line selection signal to sequentially select any one of a plurality of gate lines GL. A plurality of TFT's connected to the selected gate line GL are turned on to apply video signals stored in the shift register of the data driver 8 to the source terminal of the TFT, thereby displaying the video signals on the liquid crystal display panel 12. Thereafter, the operation as mentioned above is repeated to display the video signals on the liquid crystal display panel 12.
In FIG. 2, the liquid crystal display panel 12 includes a thin film transistor (TFT) arranged at each intersection between the gate lines GL and the data lines DL, thereby functioning as a switch. A pixel electrode 14 is arranged between a pre-stage gate line GL-1 and the TFT.
The TFT functions as a switch that loads and breaks a signal voltage onto and from a pixel electrode 14. A gate terminal of the TFT is connected to the gate line GL, and a drain terminal of the TFT is connected to the pixel electrode 14. The pixel electrode 14 includes a storage capacitor Cst provided between the pre-stage gate line GL-1 and the drain terminal of the TFT, and a liquid crystal cell Clc connected between the drain terminal of the TFT and a common voltage terminal Vcom at an upper substrate (not shown). The pixel electrode 14 is an area that transmits and shuts off light. The pixel electrode 14 applies a data voltage to a liquid crystal layer (not shown), thereby displaying image data. Accordingly, a pixel voltage is applied to the pixel electrode 14 to display image data. The storage capacitor Cst improves a sustaining characteristic of a liquid crystal application voltage, thereby stabilizing a gray scale display and maintaining a pixel information during a non-selection interval of a pixel. The storage capacitor Cst charges a data voltage from the pre-stage gate line GL-1 upon scanning of the gate line GL.
In FIG. 3, the storage capacitor Cst charges a positive voltage during an 1H interval when a scanning pulse is turned ON. The voltage charged on the storage capacitor Cst is maintained during 1 frame after a scanning pulse was turned OFF. However, a method of driving a liquid crystal display device using the storage capacitor Cst connected to the pre-stage gate line GL-1 has a problem in that a high voltage at the pre-stage gate line GL-1 is derived into the storage capacitor Cst upon data charging of the storage capacitor Cst into the gate line GL and added to a pixel voltage. For example, when a gate voltage is 20V, a derived voltage ΔV having a very high value of about 10V is applied to the pixel. Since the voltage applied to the pixel is a combination of the derived voltage ΔV and a charged voltage Vpixel, image data displayed on the liquid crystal display panel 12 is distorted. Moreover, since the applied voltage is approximately three times larger than a normal voltage applied to a normal pixel, a liquid crystal layer is subjected to a large liquid crystal displacement. Accordingly, such a liquid crystal displacement results from a rising time as given by the following equation:
                              Rise          ⁢                                          ⁢          Time          ⁢                                          ⁢                      (                          τ              ON                        )                          =                                            r              1                        *                          d              2                                                          ɛ              0                        *            Δ            ⁢                                                  ⁢            ɛ            *                          (                                                V                  2                                -                                  V                  th                  2                                            )                                                          (        2        )            
A variation of the rising time influenced by the pre-stage gate line GL-1 when a charged voltage Vpixel is 5V is indicated by the following equation:
                              Rise          ⁢                                          ⁢          Time          ⁢                                          ⁢                      (                          ϑ              ON                        )                          =                                            r              1                        *                          d              2                                                          ɛ              0                        *            Δ            ⁢                                                  ⁢            ɛ            *                          (                                                15.0                  2                                -                                  1.0                  2                                            )                                                          (        3        )            wherein, if there is an effect of the pre-stage gate line GL-1, Vth=1.0V and ΔV=10V.
As previously described, the pixel voltage V is 15V because it is an addition of the derived voltage ΔV to the charged voltage Vpixel, due to the effect of the pre-stage gate line GL-1. Since the rising time τON is inversely proportional to a square of the pixel voltage V, the rise time increases rapidly. Accordingly, a liquid crystal response increases, thereby causing liquid crystal displacement. This sudden liquid crystal displacement causes a brightness change per frame, thereby generating a flicker phenomenon.